How does pipeline adc work

This paper studies all the sub-block circuits of pipeline ADC first, and then come up with all the constraints and limitations for all the circuitry in term of speed and noises. Then a system level speed and power trade off consideration is explored in order to optimize the overall performance. As verification of the proposed design methodology, a bit 40MHz pipeline analog-to-digital converter prototype is developed in commercial TSMC 90nm CMOS technology: using op-amp sharing, dynamic biasing methods, it works in two modes: pipelined ADCs for high speed, cyclic ADC for low speed only last stage runs, other stages are power off to save power.

For pipeline mode, the total power consumption decrease as the sampling frequency drops. Skip to main content. Email Facebook Twitter. Abstract Demand for high-performance analog-to-digital converter ADC integrated circuits ICs with optimal combined specifications of resolution, sampling rate and power consumption becomes dominant due to emerging applications in wireless communications, broad band transceivers, digital-intermediate frequency IF receivers and countless of digital devices.

For improved accessibility of PDF content, download the file to your device. Thumbnails Document Outline Attachments. Highlight all Match case. Whole words. Toggle Sidebar. Zoom Out. More Information Less Information. Enter the password to open this PDF file:. Cancel OK. File name: -. File size: -. We will consider three applications: 1 wideband wireline,2 wireless broadband and 3 high-resolution narrow bandwidth wireless.

Examples of such applications are Powerline Communications and Cable Modem. The Pipeline ADC is ideally suited for these applications. Special consideration should also be given to the fact that the input signal is a composite multitone OFDM signal and not a simple sine-wave, as has traditionally been used to specify ADCs. The multi-tone nature of OFDM signals means this signal is in fact composed by a multitude of low-amplitude sinewaves and this has a major impact for example in relaxing the required sampling clock jitter.

So the architecture choice here is based mainly on system level architecture. In this case, the choice depends more on the customer preference and the possible need for compatibility with higher bandwidths in the future, which might tend to favour a Pipeline ADC.

Choosing the correct ADC is a crucial step in designing the optimum receive path, and attention must be paid to accurately specifying the ADC by taking the full system into consideration. The information provided in this article should prove useful in making this selection. No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse. Design And Reuse.

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